It has been just a few days since the Shakti processor has been announced. The project funded by the Indian Ministry of Electronics and Information Technology is now ready for app development. The Indian Institute of Technology (IIT) Madras has released the SDK for its open-source Shakti processor that’s based on RISC-V instruction set architecture. IIT Madras also revealed that the development board will release in the near future as well.
Work on the Shakti processor began in 2016 by the RISE Group at IIT Madras and they aim to release up to six classes of processors that will be targeted at different markets. RISE promises that these processors would be able to compete with commercial chipsets in terms of area, performance and power consumption.
Like China and those in the European Union, India is also displaying interest in designing its own processors instead of depending on those designed in the US. By releasing the Shakti SDK, developers can start building apps for it even before it is made commercially available.
As per a report by Tom’s Hardware, the various processor classes are as follows:
E Class: This is a 3-stage in order that’s targeted at embedded devices such as IoT, robotics, motor controls and the like.
C Class: It is a 32-bit 5 stage in-order microcontroller-class of processors supporting 0.2-1 GHz clock speeds that are aimed at midrange application workloads and has a very low power profile. There’s also support for optional memory protection.
I Class: It is a 64-bit out of order processors that support clock speeds ranging from 1.5-2.5GHz. It also supports multi-threading and targets mobile, storage and network apps.
M Class: It supports multi-core processors up to eight CPU cores which can also include I and C class cores.
S Class: This is aimed at the workstation and server-type workloads and it is an enhanced version of the I Class processor that features multi-threading support.
H Class: This is primarily for high-performance and analytical workloads. The main feature here includes high-single thread performance, optional L4 cache and Gen-Z fabric and storage class memory.
It is also reported that the RISE Group is also working on two experimental classes of processors. The report states, “The first is the T class, which should support object-level security and coarse grain tags for micro-VM-like functionality to mitigate software attacks like buffer-overflow. The second is the F class, which can be thought of as an upgrade over the T class with additional support for redundant compute blocks and bus fabrics, ECC memory and functionality to detect permanent faults.”...