Washington: Researchers, including one of Indian-origin, claim to have developed the highest-performing carbon nanotube transistors ever, paving the way for flexible electronics with longer battery life. The technology developed by University of Wisconsin-Madison materials engineers could also have specific uses in industrial and military applications.
Michael Arnold, Professor Padma Gopalan and their students reported transistors with an on-off ratio that is 1,000 times better and a conductance that is 100 times better than previous state-of-the-art carbon nanotube transistors. "Carbon nanotubes are very strong and very flexible, so they could also be used to make flexible displays and electronics that can stretch and bend, allowing you to integrate electronics into new places like clothing," said Arnold.
"The advance enables new types of electronics that aren't possible with the more brittle materials manufacturers are currently using," Arnold added. Carbon nanotubes are single atomic sheets of carbon rolled up into a tube. As some of the best electrical conductors ever discovered, carbon nanotubes have long been recognised as a promising material for next-generation transistors, which are semiconductor devices that can act like an on-off switch for current or amplify current.
This forms the foundation of an electronic device. The team drew on cutting-edge technologies that use polymers to selectively sort out the semiconducting nanotubes, achieving a solution of ultra-high-purity semiconducting carbon nanotubes. Previous techniques to align the nanotubes resulted in less-than-desirable packing density, or how close the nanotubes are to one another when they are assembled in a film.
However, the researchers pioneered a new technique, called floating evaporative self-assembly, or FESA. Researchers exploited a self-assembly phenomenon triggered by rapidly evaporating a carbon nanotube solution.
The team's most recent advance also brings the field closer to realising carbon nanotube transistors as a feasible replacement for silicon transistors in computer chips and in high-frequency communication devices, which are rapidly approaching their physical scaling and performance limits. The research was published in the journal ACS Nano.
